Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. A transistor is an element that is utilized extensively in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET).
The gate dielectric for MOSFET devices has in the past typically comprised silicon dioxide. However, as devices are scaled down in size, silicon dioxide becomes a problem because of gate leakage current, which can degrade device performance. Therefore, there is a trend in the industry towards the development of the use of high dielectric constant (k) materials (e.g., having a dielectric constant of 3.9 or greater, for example) for use as the gate dielectric in MOSFET devices.
High k gate dielectric development has been identified as one of the grand challenges in the 2003 edition of International Technology Roadmap for Semiconductor (ITRS), incorporated herein by reference, which identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. For low power logic (for portable electronic applications, for example), it is important to use devices having low leakage current, in order to extend battery life. Gate leakage current must be controlled in low power applications, as well as sub-threshold leakage, junction leakage, and band-to-band tunneling. For high performance (namely, speed) applications, it is important to have a low sheet resistance and a minimal effective gate oxide thickness.
To fully realize the benefits of transistor scaling, the gate oxide thickness needs to be scaled down to less than 2 nm. However, the resulting gate leakage current makes the use of such thin oxides impractical in many device applications where low standby power consumption is required. For this reason, the gate oxide dielectric material will eventually be replaced by an alternative dielectric material that has a higher dielectric constant. However, device performance using high k dielectric materials suffers from trapped charge in the dielectric layer, which deteriorates the mobility, making the drive current lower than in transistors having silicon dioxide gate oxides, thus reducing the speed and performance of transistors having high k gate dielectric materials.
FIG. 1 shows a cross-sectional view of a prior art semiconductor device 100 comprising a transistor with a high k gate dielectric material. The semiconductor device 100 includes field oxide regions 104 formed in a workpiece 102. The transistor includes a source S and a drain D that are separated by a channel region C. The transistor includes a gate dielectric 108 that comprises a high k insulating material. A gate 110 is formed over the gate dielectric 108, as shown.
After the gate 110 is formed, the source region S and drain region D are lightly doped, e.g., by a lightly doped drain (LDD) implant, to form extension regions 128 of the source S and drain D. Insulating spacers 112 are then formed along the sidewalls of the gate 110 and gate dielectric 108, and a source/drain implant is performed on exposed surfaces of the workpiece 102, followed by a high temperature thermal anneal, typically at temperatures of about 1000 to 1015° C., to form the source S and drain D.
One problem with the prior art semiconductor device 100 shown in FIG. 1 is that an interfacial oxide 114 is formed between the workpiece 102 and the high k dielectric 108, and an interfacial oxide 116 is formed between the high k dielectric 108 and the gate 110. The interfacial oxides 114 and 116 form because the workpiece 102 typically comprises silicon, which has a strong tendency to form silicon dioxide (SiO2) in the presence of oxygen, during the deposition of the high k dielectric 108, for example, forming interfacial oxide 114. Likewise, the gate 110 often comprises polysilicon which also tends to form SiO2 116 on the top surface of the high k gate dielectric 108.
The source S and drain D regions of the semiconductor device 100 are formed by implanting ions of a dopant species, and annealing the workpiece 102 to cause diffusion of the dopant deep within the workpiece 102, forming the source S and drain D regions. One problem with the prior art structure 100 is that the high temperature anneal processes used to form the source S and drain D tend to degrade the dielectric constant of the high k gate dielectric 108. In particular, when exposed to a high temperature treatment, the interfacial oxides 114 and 116 have become thicker, increasing the effective oxide thickness (EOT) 118 evaluated electrically from the entire gate stack (the interfacial oxide 114, high k dielectric 108 and interfacial oxide 116) of the semiconductor device 100. Thus, by using a high k dielectric material for the gate dielectric 108, it can be difficult to decrease the gate dielectric 108 thickness to a dimension required for the transistor design, as devices 100 are scaled down in size.
Another problem with the prior art semiconductor device 100 shown in FIG. 1 is that by forming the source S and drain D using ion implantation, it is difficult to meet the reduced junction depth Xj and sheet resistance Rs, that are required for advanced technologies. The thicker the junction depth Xj, the more the short channel effects such as the hot carrier effects become severe and degrade transistor reliability, causing source S and drain D leakage and/or punch-through. Furthermore, the device 100 has a high sheet resistance Rs, which degrades drive current and circuit speed, thus making the semiconductor device 100 less reliable for use in high-performance and/or high-speed applications.
Therefore, what is needed in the art is a transistor design and fabrication method, wherein the effective gate dielectric thickness, the junction depth, and the sheet resistance are reduced.